Conventional semiconductor devices typically are made up of a semiconductor substrate, normally a monocrystalline silicon with a plurality of dielectric and conductive layers formed on it. An integrated circuit is formed of semiconductor devices connected by a set of spaced-apart conductive lines and associated interconnection lines, such as bus lines, word lines and logic interconnection lines. Such interconnection lines generally constitute a limiting factor in terms of various functional characteristics of the integrated circuit. There exists a need to provide a reliable interconnection structure capable of achieving higher operating speeds, improved signal-to-noise ratio, improved wear characteristics, improved reliability while at the same time reducing the dimensions of the circuit elements to increasingly smaller size.
Most interconnection lines in the past have been made of aluminum or aluminum-based alloys. The performance of a semiconductor device could be improved by forming the interconnection line of a metal having a higher conductivity than aluminum, thereby increasing current handling capability. It is known that copper, copper-based alloys, gold, gold-based alloys, silver and silver-based alloys generally exhibit a higher conductivity than aluminum and aluminum-based alloys, but each has its own drawbacks. One drawback of using copper, for example, is that copper readily diffuses through silicon dioxide, the typical dielectric material employed in the manufacture of semiconductor devices. Moreover, a low cost satisfactory method for etching copper has yet to be developed.
One method of forming copper interconnection lines is by using a “damascene” technique. Damascene is a process which has been employed for centuries in the fabrication of jewelry, and has recently been adapted for application in the semiconductor industry. Damascene basically involves the formation of a trench or a channel in a planarized insulating layer. That opening is filled with a metal to form a channel and any remaining metal material is polished from the surface of the insulating layer. The traditional etch back technique of providing an interconnection structure involves depositing a metal layer, forming a conductive pattern with interwiring spacings, and filling the interwiring spacings with dielectric material. Thus, damascene differs from the traditional etch back technique by forming a pattern of openings in a dielectric layer that are filled in with metal to form a conductive pattern followed by planarization.
In a “dual damascene” technique, in addition to the etched trench or channel (line) in the dielectric, additional holes known as vias are etched at specific locations in the bottom of the trenches. These vias are openings to lower level circuit elements which are buried in the dielectric. In the dual damascene technique, the trench and the via extending down from the trench are filled with conductive metal in a single step. This is a cost saving measure and also can increase both the process yield as well as the qualities of the electrical connections in the circuit.
According to conventional practices, a plurality of conductive layers are formed over a semiconductor substrate, with the uppermost conductive layer joined to a bonding pad for forming an external electrical connection. In a copper interconnection process, conductive layers would be formed by either damascene or dual damascene techniques. The uppermost conductive layer of the integrated circuit which is to be connected to the chip carrier is typically referred to as the wire bonding layer. The wire bonding layer has bonding pads which are used to make external connections by means of electrically conductive wires and external connection electrodes.
The most commonly used materials for the wire bonding layer are aluminum or aluminum-based alloys, such as aluminum with 2% copper. A bonding tool coupled to a bonding machine connects the bonding pads with external connection electrodes using electrically conductive wires. The electrically conductive wires are bonded to the bonding pads by the bonding tool using ultrasonic and thermal energies.
A suitable conductive barrier layer is needed between the copper interconnection lines and both the surrounding dielectric and any other metallic contacts it might make. Such a barrier layer can be conveniently formed by employing a material that is substantially impervious to the diffusion of impurities into the copper interconnection lines and to the diffusion of copper atoms into the dielectric or nearby metal contacts. It is well known that titanium nitride (TiN) is a suitable conductive barrier material for copper. However, in the copper interconnection processes, conventional tantalum nitride (TaN) is the most commonly used conductive barrier material. Besides TaN, tantalum silicon nitride (TaSiN) can also be used as a conductive barrier material for the copper interconnection processes. The use of TiN would require additional deposition chambers because the deposition of TiN and TaN cannot be performed using the same deposition chamber. The need for additional deposition chambers for TiN deposition undesirably increases the cost and process complexity for the production of semiconductor devices.
Conventional TaN used in interconnect applications as a diffusion barrier for Cu has a nitrogen-to-tantalum ratio of slightly under 1.0. It typically contains a nitrogen content by atomic weight of 20%. U.S. Pat. No. 6,117,769 illustrates a barrier layer used to reduce diffusion of Al into Cu formed from TaN having a somewhat higher fraction of N, in the range of 1.0 to 1.2. This corresponds to a range of 30% to 40% by weight. The foregoing composition produces a layer that is said to be satisfactory for limiting Al diffusion at a TaN in a thickness of as low as 50 nm.